The present invention relates to the field of high-performance, multiprocessor computer systems which are using an optimized Input/Output (I/O) subsystem that is based on dedicated System Assist Processors (SAPs) or I/O Processors (IOPs). These I/O processors perform communication between multiple Central Processing Units (CPUs) and many peripheral I/O devices attached via multiple I/O channel paths, e.g., for database business applications. More specifically, the present invention relates to processing I/O requests issued by the SAPs, and particularly, to how a request response issued by the I/O periphery is processed in the multiprocessor system.
An exemplary non-uniform multiprocessor computing system of the above mentioned shape is described in GB Application No. 2454996 A, which teaches a method for the balanced handling of inbound initiatives. In this context, an “initiative” is to be understood as a response to a former initiated I/O operation or as a request coming from an I/O device via an I/O path. Such a response is typically signalled via an I/O interrupt. In the prior art method these are the interrupts from the channels to the firmware running on the I/O processors.
A shortcoming of this prior art method is that with an increasing number of I/O processors the handling of initiatives leads to increased cache traffic and contention due to shared data structures, which slows down the initiative handling significantly. Further, it leads to increased firmware path length and control block contention due to an increasing number of processors detecting the same initiative at the same time, but only one processor is finally handling it.
Any potential solution to these n-way effect shortcomings would have to meet the following requirements: The initiatives need to be handled with as little cache and control block contention and overhead as possible, but peak or unbalanced workloads still need to be handled without any bottlenecks on one or some processors of the system.